The invention relates to a phase detector, a phase detection method and a PLL (Phase-Locked Loop) using the phase detector, and more particularly a phase detector using a high-frequency clock as a trigger signal to make the control signals UP and DN overlap with each other, and a PLL using the phase detector in order to reduce the jitter.
FIG. 1 shows a block diagram of a conventional PLL. The PLL is for providing a recovery clock that is phase synchronized with the input signal (IN). For example, when the data of an optical disk medium is read, the PLL is utilized to lock the phase and frequency of the EFM (Eight-to-Fourteen Modulation) signal and to output a phase locked clock (PLCK) as a sampling clock for the EFM signal or a reference clock for other controls. Referring to FIG. 1, the conventional PLL 10 includes a phase detector 11, a charge pump 12, a loop filter 13, a VCO (Voltage Control Oscillator) 14, and optionally a frequency divider 15.
The phase detector 11 is used to detect a phase error between an input signal IN and a phase locked clock PLCK2, and output control pulses UP and DN to control the charge pump 12 according to the phase error. For example, when the phase of the phase locked clock PLCK2 leads that of the input signal IN, the width of the control pulse UP outputted from the phase detector 11 is smaller than that of the control pulse DN so that the charge pump 12 generates a negative control current Icp. At this time, the loop filter 13 reduces the control voltage Vct1 according to the negative control current Icp and thus lowers the frequency of the phase locked clock PLCK1 outputted from the VCO 14. On the contrary, when the phase of the phase locked clock PLCK2 lags behind that of the input signal IN, the width of the control pulse UP outputted from the phase detector 11 is larger than that of the control pulse DN so that the charge pump 12 generates a positive control current Icp. The loop filter 13 increases the control voltage Vct1 according to the positive control current Icp, and thus increases the frequency of the phase locked clock PLCK1 outputted from the VCO 14.
FIG. 2 shows a conventional circuit of a phase detector, a charge pump, and a loop filter of the PLL. Referring to FIG. 2, the phase detector 11 includes three flip-flops 111, 112 and 113, and two XOR (Exclusive OR) gates 114 and 115. The flip-flop 111 uses the input signal IN as its input signal and outputs its output signal to the input terminal of the flip-flop 112. The output signal of the flip-flop 112 is outputted to the input terminal of the flip-flop 113. The flip-flops 111, 112 and 113 use the phase locked clock PLCK2 as the trigger signal, wherein the flip-flop 111 is of the negative-edge trigger type and the flip-flops 112 and 113 are of the positive-edge trigger type. The XOR gate 114 receives the input signal IN and the output signal of the flip-flop 112, and generates the control pulse UP. The XOR gate 115 receives the output signals of the flip-flops 112 and 113 and generates the control pulse DN. The charge pump 12 includes two current sources IUP and IDN, and two switches S1 and S2. The control pulses UP and DN respectively control the switches S1 and S2 so as to generate the control current Icp. The loop filter 13 includes two capacitors C1 and C2 and a resistor R1. The loop filter 13 receives the control current Icp and then generates the control voltage Vct1.
FIG. 3 shows waveforms of some signals of the circuit in FIG. 2, including the input signal IN, the oscillation clock PLCK2, the control pulses UP and DN, and the control voltage Vct1 when the PLL is at the phase locked state. As shown in FIG. 3, because the control pulses UP and DN are not overlapped, the control voltage Vct1 is still changed periodically and transiently even though the PLL has reached the phase locked state. Thus, the oscillation clock outputted from the VCO 14 has jitters.